Verilog code for D Flip Flop
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7: Design a negative edge-triggered D-flip flop (D FF) with synchronous clear active high (D FF clears only at a negative edge of the clock when clear is high). Use behavioral statements only. (Hint: Output q of DFF must be declared as reg). Design a clock with a period of 10 units and test the D FF.8: Design the D-flip flop in exercise 7 with asynchronous clear (D FF clears whenever clear goes high. It does not wait for the next negative edge). Test the DFF.
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