Design-Reuse

Optimization Methodologies for Cycle-Accurate SystemC Models Converted from RTL VHDL

IP design-houses are hard-pressed by their customers to provide SystemC models of their portfolio IPs, despite already existing VHDL views. VHDL IPs can be translated to SystemC, ensuring correctness, ...
EDN

Accellera VHDL Standard

In July 2006, the Accellera board approved a revision VHDL standard (revision 1076-2006-D3.0) put forward by the Accellera VHDL Technical Subcommittee (VHDL TSC). As an Accellera standard, revision ...
Semiconductor Engineering

Improving VHDL

For the past several years, I have had the privilege to chair the IEEE 1076 VHDL working group. In March, we handed off the revisions to the VHDL LRM to our technical editor to finalize the document ...
EDN

VHDL, Verilog models available for Spansion flash

SAN FRANCISCO — Free Model Foundry (FMF), an open source model warehouse and design services company promoting development and distribution of simulation models of electronic components, announced ...